Monthly Archives: July 2014

What is the Optimal Logic Depth Per Pipeline Stage?

There are two things that affect the performance: cycles per second (clock rate, frequency), and instruction per cycle (IPC).

The way to increase the frequency is: 1) faster transistor through process generations, and 2) less logic in each pipeline stage (evaluated by #FO4 delays).

This seminal paper assumes that the context is within a particular process generation, that is the FO4 delay stays the same. Continue reading